1. Field of the Invention
The present invention relates to a device and a process for debugging a program to be run by a programmable controller.
2. Description of the Background
SFC (Sequential Function Chart) is a programming language which allows a program running procedure and conditions to be clearly represented, by dividing the sequence of a program into a plurality of steps in a flowchart format. An SFC may be utilized to represent a program for a programmable controller (hereinafter referred to as the "PC") which program-controls an object to be controlled. The development of a debugging device and a debugging process that facilitates more effective program writing is desired in order to permit the SFC type program to be used in a wide variety of applications. A "step break method" is one of the conventional debugging processes used with a debugging device for SFC-based programs in PC applications.
FIG. 10 is a block diagram illustrating a CPU module of the PC and a peripheral device for writing a program for the PC, for debugging the program written, for monitoring the program when it is run, and for other purposes. In FIG. 10, the numeral 1 indicates a CPU module of the PC, comprising an input section 2 through which data is entered from other modules (not illustrated), an operation section 3 for performing data operations, an output section 4 for outputting data to other modules (not illustrated), a power supply section 5 acting as the power supply of the entire module, an SFC program storage 6 for storing an SFC program which corresponds to the program being run by CPU 1, and a data storage 7 for storing data incoming from a peripheral device 8 and exchanging information with the SFC program storage 6. The peripheral device 8 has structure to perform a program writing function, a written program monitoring function and a debugging function, and includes a step break information table 12 for storing information on step breaks for program debugging.
FIG. 11 shows the contents of the step break table 12 comprising block numbers 12A, break step numbers 12B and cycles 12C. FIG. 12 gives an SFC program example, and FIG. 13 is a flowchart illustrating a step break processing procedure.
As shown in FIG. 12, the SFC program is made up of blocks 20 to 24. Each block includes at least (i) an initial step 30, which indicates the beginning of the block; (ii) basic steps 31, which are basic units within a block comprising execution units of the SFC program; (iii) transition conditions 32, which are the conditions of transition to the next step; (iv) block driving steps 33 for starting another block; and, (v) an end step 34 for declaring that a series of block processings has been completed. The group from the initial step 30 to the end step 34 is referred to as a "block". In a current program environment, a maximum of 256 blocks, e.g., (0) to (255), can exist in a SFC program. Conventionally, block (0) is referred to as a "main block" 20, from which the run of the SFC program begins. Within any of the blocks, another block may be specified by a user at the block driving step 33 and the run of the program will shift to the specified block. In the initial step 30, at basic steps 31 and transition conditions 32, the corresponding detailed sequence programs of a PC may be written using ladders or the like.
As shown in the SFC program example of FIG. 12, the main block 20, i.e., Block 0, includes a selective branch 35. The selective branch will execute only a step where a transition condition has been first enabled among a plurality of steps 31 connected in parallel. Also included is a selective connection 36 for terminating the processing performed by the selective branch 35. In an operation of the program, beginning with the main block 20, step (1) is first executed. After the step (1) 31 is executed, selection processing is performed because of the transition condition 32. The condition leads to four block driving steps (1)-(4). By executing any one of the block driving steps (1) to (4), any of the routes starting from corresponding Block (1), (2), (3), or (4) is executed. When any of the Blocks (1), (2), (3) and (4) has been selected, the steps in the selected Block are executed in order from the initial step 30 to the end step 34. When the end step 34 has been executed, the program execution returns to the initial step 30 of Block (0) and forces a block driving step 33 to be executed starting from the next transition condition. After any of the steps (2), (3), (4) and (5) has been executed, the step (6) is processed. When the end step 34 is executed, the program execution returns to the initial step 30 again and the series of operations is then repeated. Instead of the above simple description of the SFC, a more complex operation may be conducted, as would be apparent to one of ordinary skill in the art.
The establishment and operation of a step break process, one of the known debugging processes, will now be described in reference to the flowchart shown in FIG. 13 and the illustrations in FIGS. 10-12. In the establishment of a step break process by the peripheral device 8, a start is first effected at step 200. Any previously existing step break information is read from the data storage 7 of the PC CPU module 1 into table 12 of the peripheral device 8, at step 201. Then, at step 202, the user determines whether or not totally new data on step break points (i.e. a whole new table) is to be registered into the step break information table 12 or whether simple additions or corrections alone are desired. When totally new data is to be registered, at step 203, the user registers in table 12 the block numbers 12A at which a break is desired to occur, the step numbers 12B at which a break is desired to occur, and the numbers of cycles 12C after which a break is desired to occur at the specified step. The new data is registered in place of the previously written data in the step block information table 12, which was read from memory 7 at the step 201. If the user determines that all new data is not to be registered, then the process proceeds directly to step 202A. At step 202A, a determination is made as to whether or not corrections should be made to the existing data. When only corrections are to be made to the existing data, the user corrects, at step 204, the block numbers 12A at which a break is desired to occur, the step numbers 12B at which a break is desired to occur, and/or the numbers of cycles 12C after which a break is desired to occur at the specified step. When corrections are not made to the existing data, or after completion of step 204, the contents of the step break information table 12 are then written into the data storage 7 of the PC CPU module 1, at step 205.
The processing of the PC CPU module 1 is then performed. First, the step break operation is started at step 206 and the PC program is run. The operation section 3 compares, at step 207, the data in the data storage 7, i.e., the blocks 12A and steps 12B in the step block information table 12, with the current run state of the SFC program stored in the SFC program storage 6, i.e., the current blocks and steps which correspond to the current portion of the PC program being run. If they do not match, the step 207 is repeated until they match. When they match, the step break operation is stopped at the corresponding step, at step 208, to terminate the processing.
The blocks 12A, the steps 12B in those blocks and the numbers of cycles 12C which are step break points registered into the step break information table 12, may be set as required. Ordinarily, the step break points should be provided at important points on a route other than the desired route, in order to check for a deviation from the desired route. However, the step break points may be strategically provided on a normal (desired) route to confirm that the normal route has been executed properly, thereby enhancing the debugging of the SFC program.
For example, assume that the step break information table is established as shown in FIG. 11 and is to be compared to the SFC program being run by CPU 2 in FIG. 12. Also assume that during the program's first cycle, it passes to Block 2; in the 2nd cycle, it passes to Block 3; and, in the 3rd cycle, it passes to Block 4. If the above sequence is the "normal route", then break points would be set on step 1 of each of Blocks 1, 3 and 4 in the 1st cycle, because a deviation from the "normal route" through Block 2 would be detected. Also, for similar reasons, break points are set on step 1 of each of Blocks 1, 2 and 4 in the 2nd cycle. For a different reason, explained subsequently, a break point is set on step 5 of Block 0 in the 3rd cycle. Thus, if a step break operation is performed when step break points are set on the above step break information table, and if it is run normally, step break will not occur either in the 1st or 2nd cycle, but it will occur at step 5 of Block 0 in the 3rd cycle. Specifically, a step break will occur after Block 4 is performed, thus confirming that up to the 3rd cycle, the program is run normally.
Nonetheless, the extensive use of step break points for debugging will result in programming inefficiencies. For example, when using the conventional SFC program debugging process as described above, a step break must be set at each pertinent branch point to check the route passed for each branch process in an SFC program. This causes the number of set breaks to increase as the number of branch processings increases, resulting in a cumbersome debugging process for the SFC program.
It is, accordingly, an object of the present invention to overcome the disadvantages in the conventional process by providing an SFC program debugging process which does not require step break setting and ensures ease of checking executed routes.